FPGA-based high-frequency clock frequency and distribution of design

With applications to high speed, low power and low voltage direction of development, circuit design have become increasingly demanding traditional IC design technology is unable to meet the increasing performance of machine systems. Also, because the level of IC design and process technology improvement, integrated circuits, increasing the size, complexity is increasing. Now the whole system can be integrated on a chip, that is, system on chip (Systemon aChip abbreviated as SOC), such a chip to have a system-level performance of complex programmable logic device (CPLD) and field programmable gate array (FPGA) as the chief representative. Main achieved with the combination of the CPLD logic function compared to, FPGA mainly used to implement sequential logic functions. For ASIC design, the use of FPGA in the realization of miniaturization, integration and high reliability systems also can reduce risk, reduce costs, shorten the development cycle.

FPGA-based high-frequency clock frequency and distribution of design

2 System hardware components

This article describes the clock board was mainly due to PET (positron emission tomography) provide front-end electronics module 32 system clock (62.5MHz) and 32 synchronous clock (4MHz). The deviation between the clock signals required within 2ns. In order to eliminate the deviation between the clock signals from various quarters, the paper describes the use FPGA to implement the main clock frequency, zero-delay output and distribution, while using multiple clock LVDS technology to achieve the realization of the transmission method. Figure 1 is a schematic diagram of its hardware design.

Can see from Figure 1, the clock circuit of the specific works is: first of all by the precision 62.5MHz crystal oscillator clock signal, and then by the clock driver chip CY2305 clock input FPGA chips GCLK pin as clock source. The clock in the FPGA chip by the DLL (delay locked loop) modules were generated system clock and 62.5MHz 4MHz synchronous clock LVTTL level signals, and then by the internal IOB (input and output function blocks) assigned to the output lead 64 feet (32 and 32 62.5MHz 4MHz system clock synchronized clock), this 64 LVTTL level signals 22 into the 32 LVDS (two-way) drive conversion chip, you can convert the LVDS signals and twisted by differential wire transfer to the front-end electronics module, 32 digital circuit boards.

2.1 FPGA Structure

Cell-type FPGA consists of three components: configurable logic block CLB (Configurable LogicBlock), input, output module I / OB and programmable connection PI (ProgrammableInterconnect). For different specifications of chips that can contain the 8 × 8,20 × 20,44 × 44 and even 92 × 92 個 CLB array, and with 64,160,352, or 448 I / OB, and for the realization of a programmable connection necessary for other parts. Figure 2 shows the design of chips used in XC2S30 internal structure.

2.2 Xinlinx's SpartanII series FPGA

Xinlinx company's current production of two types of FPGA products a class representative is XC40003/Spartan series other is Vir-tex/SpartanII series. In addition to these two types of products have three basic resources FPGA (programmable I / O, programmable logic blocks CLB and programmable wiring, etc.) outside also has on-chip RAM resources. But the two products are different. FPGA-based high-frequency clock frequency and distribution of design which can be used to implement the chip XC4000E distribution of RAM, also specifically for the realization of a programmable system on chip development Virtex series, the distribution of its on-chip RAM and block RAM are met, and can on-chip system for the other properties, such as clock distribution and characteristics of multi-level interface. SpartanII series compared with the Virtex series, in addition to Virtex block RAM is less than the number of products, the other relevant properties (such as a typical door range, line width, metal layer, the core voltage within the chip input and output pin voltage, system frequency and the number with DLL, etc.) are basically the same, it's an outstanding feature (and use the chips in this design the main reason) is: This series is designed to replace the mask gate array of low-cost FPGA, the number reaching the gate array , its price, compared with gate arrays. Therefore, this article describes the design of the clock circuit used SpartanII Series FP-GA in XC2S30-5PQ208 chip to achieve.

3 Implementation with FPGA clock frequency and distribution of

Shown in Figure 2 SpartanII series chip with four all-digital delay locked loop (DLL), each DLL can drive two global clock distribution network. DLL output clock by controlling a sample can compensate for the clock delay caused by wiring the network, thereby effectively remove the device from an external input port to an internal delay of each clock load. DLL In addition to providing the user input clock beyond the zero time delay, also has the function of the clock multiplier and divider. It can be the source of the clock and a two-octave frequency 1.5,2,3,4,5,8 or 16 points. This design is the use of DLL's zero delay and frequency functions to achieve the output of the 62.5MHz clock frequency and 16 minutes after the 4MHz (about) clock output. FPGA-based high-frequency clock frequency and distribution of design

3.1 Digital delay locked loop (DLL) of the structural principle

Figure 3 is a block diagram of internal DLL, which consists of various types of clock delay line and control logic of the composition. Delay line is mainly used to generate a clock input CLKIN delay. Through the device's internal clock distribution network can be assigned to the input clock for all internal registers and clock feedback side CLKFB. Control logic are mainly used for sampling the input clock and feedback clock to adjust the delay line. Delay line referred to here by the delay or attenuation of voltage-controlled delay component composition, SpartanII series chips use the latter. DLL may be in the input clock and feedback clock insertion delay between the constantly, until the rising edge of clock synchronization of two up. When the two clock synchronization, DLL lock. After the DLL lock, as long as the input clock has not changed, the two clock does not appear to recognize bias. Therefore, DLL output clock compensates for the clock distribution network to bring the input clock delay, thereby eliminating the source of the delay between the clock and load.

3.2 DLL function to achieve

SpartanII series chip contains specific DLL functions to achieve macro-cell module BUFGDLL, the structure diagram shown in Figure 4. The module consists of IBUFG, FPGA-based high-frequency clock frequency and distribution of design CLKDLL and BUFG composed of three library elements its block diagram shown in Figure 5. Figure 5, CLKDLL library DLL component used to implement the main functions of include the completion of the zero-delay clock output, clock multiplier and the frequency and mirror operation. The IBUFG and BUFG were achieving external clock input and output clock distribution to the chip pin. The design of the clock frequency is 62.5MHz clock will be input by the IBUFG by CLKDLL frequency side and then passed by the CLKDV BUFG and then by distribution to the chip-chip IOBUF general I / O output pin.

4 Software

The overall concept in the design and device selection is completed, the work must be carried out to establish the design input file, the file is mainly used to describe the design of logic circuits. Used here is the development tools provided by XILINX FOUNDATION 4.1. This design uses a hardware description language VHDL to design some of its procedures are as follows:

entity lvds is
port (
pclk: in STD LOGIC;
pclk_62: out std_logic_vector (31 downto 0);
pclk_4: out std_logic_vector (31 downto 0));
end lvds;
architecture lvds_arch of lvds is
component clkdll
port (clkin: in std_logic;
clkfb: in std_logic;
rst: in std_logic;
clk0: out std_logic;
clk90: out std_logic;
clk180: out std_logic;
clk270: out std_logic;
clk2x: out std_logic;
clkdv: out std_logic;
locked: out std_logic);
end component;
begin
reset n <= '0 ';
uibuf: ibufg port map (
i => pclk,
o => clk);
udll: clkdll port map (clkin => clk,
rst => reset_n,
clkfb => clkfb,
clk0 => clk0,
clk90 => open,
clk180 => open,
clk270 => open,
clk2x => clk2x,
clkdv => clkdv,
locked => locked
);
bufg_clk0: bufg port map (i => clk0,
o => clk_int2;
);
clkfb <= clk_int2;
process (clk2x);
begin
if clk2x'event and clk2x = '1 'then
clk_int <= clk int2;
clk_int3 <= clkdv;
pclk_62 (0) <= clk_int;
pclk_62 (1) <= clk_int;
...
...
pclk_62 (31) <= clk_int;
pclk_4 (0) <= clk_int3;
pclk_4 (1) <= clk_int3;
...
...
pclk_4 (31) <= clk_int3;
end if;
end process;
end lvds_arch;