Low-noise single-chip based on the PLL frequency divider design

VSAT is a small satellite communications systems, remote areas for families and business users with reliable, cost-effective broadband data and other services. VSAT with a small antenna to send and receive satellite signals can cover all areas in the satellite high-bandwidth connections to users, regardless of the user in the vicinity is a communications infrastructure.

The current global use of the VSAT more than 1 million, while a large number of potential users is expected. United States, about 3,000 people live in relatively remote areas, who are potential users of VSAT. In the UK, as a relatively low rate of cable laying, and telephone switching equipment distance limits ADSL (Asymmetric Digital Subscriber Line) popularity, 30% of the population are expected to develop VSAT users.

In order to enhance broadband access in rural areas, the British government is to expedite the processing VSAT uplink channel's mandate. Similarly, Europe has authorized agencies to streamline regulatory procedures for the smooth deployment of VSAT. At the same time, VSAT market, continuous development has the supply of equipment suppliers face increasing pressure, they must Jianshao the cost of VSAT systems and Jian Hua Qi use.

Figure 1 is a spectrum allocation from the European Information Network (www.efis.dk) removal of an example from which we can see that in the 3 GHz-15GHz frequency range of wireless applications. European Telecommunications Standards Institute has been assigned to high-frequency Ku-band VSAT uplink. Uplink between the work of the 14-14.5GHz, the downlink is working on 12.5-12.75GHz or between 10.7-11.7GHz. Other countries, pretty much the same spectrum allocation.

Low-noise single-chip based on the PLL frequency divider design

In order to work within these bands, VSAT designers need a stable low-noise high-frequency signal source. VSAT in the intermediate frequency (IF) band is usually 950-1,450 MHz, needs a local oscillator frequency is 13.05GHz. So far, designers are still only by frequency multiplying to produce work in this band IF source.

Figure 2 shows a standard frequency multiplier. Its principle is: a stable frequency source into the non-linear circuit, and then selectively produce the desired output harmonic. The output through strict filtering, and then re-amplified by linear amplifier, for compensation.

The higher the output harmonic series as the lower order to the reference frequency from a low-level source (such as the crystal) was increased to microwave frequencies, we need multi-level circuit. This is the disadvantage of frequency multiplier, which often make the design become very complex and expensive, and the efficiency is very low. Other hand, the multiplier also has its advantages, that is, it can achieve almost any desired frequency.

Low-cost, high-frequency PLL

A new generation of low-noise high-frequency divider for the RF chip designers a low-cost, high-performance solutions that can be used to replace the frequency multiplier. 13.5GHz frequency divider provided by Zarlink, designers can lower the cost of phase-locked loop (PLL) circuit for the Construction of VSAT and other high-frequency source RF device. Divider scalable single-chip frequency synthesizer output range, thus ensuring the high frequency of the PLL works in the relevant forward design can proceed smoothly.

Figure 3 is a fundamental frequency synthesizer circuit, which consists of a voltage-controlled oscillators (VCO), a variable divider and a phase comparator constituted.

Based on single-chip high-frequency low-noise PLL Frequency Divider Design

Added to the VCO control voltage on the decision of the VCO output frequency. Voltage generated by phase comparator with two input signals proportional to the phase difference. This voltage controls the VCO frequency, so as to ensure through the divider after the (fN) back from the VCO feedback input frequency and phase comparator reference input fr the same phase, thus ensuring the same frequency. Therefore, VCO frequency remains N × fr. This synthesizer will generate a series of intervals the frequency fr.

Single-chip frequency synthesizer is usually limited to the maximum extent 2-3GHz, on the one hand is affected by the market, on the other hand because the frequency is too high power consumption when the synthesizer will be excessive. In order to generate high-frequency source, usually in the PLL synthesizer with a separate external crossover coupling. The crossover frequency of the source will be "pre-points" to a deal by the frequency synthesizer.

PLL cheap, but so far, their maximum frequency by the low noise limit the frequency response of commercial crossover.

13.5GHz frequency divider listing, designers can use low-cost standard components to build PLL, thereby providing the necessary VSAT and other high-frequency RF devices.

Figure 4 shows how to use the PLL circuit to create a VSAT uplink local oscillator. The design requires a better noise performance single-chip frequency synthesizer, such as the SP5769. The chip's maximum operating frequency of 3GHz, but the device will be through the ZL40813 13.5GHz VCO output divided by 8 after (for 1.6GHz), the frequency can be extended to 13.5GHz. SP5769 1.6GHz input frequency was further divided, and then with the crystal reference frequency compared. SP5769's output through a charge pump, VCO control input, to form a closed loop.

Based on low-noise single-chip design of high-frequency divider of the PLL

The circuit can also use other single-chip frequency synthesizer, but should be selected who can interface with high-frequency synthesizer prescaler.

BiCMOS technology-based synthesizer, some circuits may be relatively low operating speed, it is not well with the high frequency divider.

Indeed, low phase noise of the VSAT and other RF devices are very important. The case of the 13.5GHz frequency divider circuit using complementary silicon bipolar technology is built, Ft to 28GHz. So in the loop bandwidth the noise and the noise is very close to the carrier, will not be PLL to eliminate.

Noise series and the physical properties of materials such as GaAs and other technology itself is the noise series is higher than the carrier noise. Figure 5 lists the other 13.5GHz frequency divider in phase-noise series.

Low-noise single-chip based on the PLL frequency divider design

φn = 20log10n

Increase in the synthesis process of the phase noise can be calculated as follows:

φn = 20log10n

Which, φn phase comparator noise over basal (noise floor) of the phase noise increment, in units of dB; n is the synthesizer output frequency and phase detector comparison frequency ratio.

SP5769 noise in the phase comparator basement -148dBc/Hz. If the comparison frequency is 4MHz, and the output frequency of 13GHz, while n is 3,250. Therefore, in the loop bandwidth, phase noise than the noise in the basement of high 70dB. Assuming no other obvious source of noise, then 13GHz output signal phase noise is -78dBc/Hz.

By a similar method to the frequency band from 1.6GHz into 4MHz, also can reduce the divider phase noise generated, to reduce the noise generated by 52dB, from -140dBc/Hz to-192dBc / Hz. This value and the comparator noise is negligible compared to the basement. The same approach will be included in part of the crystal frequency noise can also be ignored.

Summary

This article describes how to use a new generation of 13.5GHz frequency divider to expand low-cost commercial synthesizer frequency range, thereby reducing the high-frequency applications, VSAT, and other new costs and promote its use.