DSP and CAN bus transmission speed and the integration of remote

Abstract: hardware system built into the structure of understanding to master the hardware, software, programming-based algorithm is developed from the main set into parts with simple and complete features, reflects the advantages of chip technology. SoC class TMS320LF2407DSP chip speed and distance transmission applications simple integrated design also reflects this.

Speed measurement is to control the project's basic problems. In many cases, long-distance transmission speed signals required. To achieve this is to use one of the main SoC (System on Chip) chip. It brought extensive changes in peripheral hardware and software on the concept. Hardware system built into the understanding of the hardware control, software programming algorithm is developed from the main into Bujian for master, with simple, integrated features, reflecting the advantages of chip technology. SoC class TMS320LF2407DSP chip speed and distance transmission applications simple integrated design also reflects this.

A related system architecture

TMS320LF2407 brought about by some event manager and the CAN controller module for the remote transmission speed and convenience provided. TMS320LF2407 have two event manager EVA and EVB, each three capture units. Corresponding to six to capture input pins CAPX (on EVA, X = 1,2,3; on the EVB, X = 4,5,6). 6 capture input pins, respectively QEPl/IOPA3, QEP2/IOPA4, IOPA5, QEP3/IOPE37, QEP4 / IOPFO and IOPFl share. When the capture input pins CAPX on the selected transition is detected, the selected GP timer count value is captured and stored in a two deep FIFO stack.

TMS320LF2407 the CAN controller module including a mailbox and the corresponding control / status registers. A total of six E-mail: 2 to receive mail (MBOX0, 1), 2 Tx-mail (MBOX4, 5), 2 which could be configured to receive or send mail (MBOX2, 3). TM $ 320LF2407 the CAN controller module fully supports CAN2.0B agreement.

Typically, the output speed sensor system is a digital speed pulse signal. Therefore, we can capture this added to the TMS320LF2407DSP chip pin. TMS320LF2407 chip capture unit using the input pulse cycle measurement, then the built-in CAN CAN bus controller unit to issue periodic signal, to achieve integration of speed and distance delivery.

2 System Configuration

2.1 Capture Unit and the configuration of the corresponding timer

TM $ 320LF2407 capture unit working principle is: to enter the pulse rising edge, falling edge or rising edge falling edge as the boundary, the corresponding timer count to measure the cycle count value is captured into the corresponding capture of a two deep stack FIF0 in. Therefore, to capture and involve the configuration of the two parts of the timer operation. Need to configure the capture operation are: the I / O port control register reuse MCRx (x = A, B, or c) in the corresponding pin is configured to capture input; in the capture control register CAPCONA / B select (enable) capture unit, select (enable) the corresponding timer and edge select (rising, falling or rising edge falling edge); in interrupt flag register EVA / BIFRX and interrupt mask register EVA / BIMRX set interrupt situation. Need to configure the timer operation are: a single general-purpose timer TXCNT cleared; in the overall general-purpose timer control register GPTCONA / B to set the appropriate operation and the timer counting direction; cycle control in a single general-purpose timer compare register is set TXPR cycle; in a single general-purpose timer control register TXCON set count mode of operation.

Abstract: hardware system built into the understanding of control of hardware, software, programming-based algorithm is developed from the main set into parts with simple and complete features, reflects the advantages of chip technology. SoC class TMS320LF2407DSP chip speed and distance transmission applications simple integrated design also reflects this.

Cycle control register TXPR comparative period is set to be greater than the input pulse cycle. Without knowing the input pulse signal period of the case, should be set to maximum. When the measurement period exceeds the maximum capture time, use the method together with the software timer overflow count solution.

2.2 out capture and transmission cycle

Capture FIFO stack stored in the capture cycle of disruption and check out there two ways. Capture Unit event manager where the interrupt latency time of 20 CPu cycles (typical), or 25 CPU cycles (the minimum protection), or 8 cPU cycle (single interrupt), or l6 a CPU cycles (not considering the memory space). In the specific design, the interrupt latency time is set to a certain value. Interrupt handler in the usual case of a short, interrupted by the interrupt latency time to time to make the main. In order to expand the system, even a single peripheral, it is to use interrupt method is better, instead of query methods.

2.3 CAN controller module and bit timer configuration

CAN controller module configuration including the initialization-mail, digital timer settings and data transceiver. See the contents of [1]. Here to introduce bit timer settings.

Bit timer setting determines bus transmission signal baud rate, is the core of CAN controller module configuration issue. TMS320LF2407 two-bit control register BCRl and BCR2. They must be CAN controller is in reset mode (ie, CCR = 1) can be configured. Bit control register BCR2 including the baud rate prescaler bit BRP [7-0], the time used to determine the CAN controller chip TQ, as the benchmark for digital control of time. Bit control register BCR2 including synchronization jump width select bit SJW [1-0], the sampling frequency select bit SAM [7], including propagation delay time (PROG SEG) and the phase delay time 1 (PHASE SEGl) time Section 1 TSEGl [3-0], decided to phase delay time 2 (PHASE SEG2) time period 2 TSEG2 [2-0].

Design Example 3

In this case the basic settings are selected Capture Unit 4 (CAP4) of the input pulse width of the capture, event manager EVB common timer 3 on the pulse count. Capture count out from the FIFO stack sent to the temporary register CAP4TEMP, in order to facilitate expansion. And then sent on the 3rd from CAP4TEMP mail sent by CANTX/IOPC6 and CANRX/IOPC7
3.1 Capture Unit for the CAN controller interrupt and query method

First of all, for system initialization, including the related interrupt, clear flag bit, 20MHz system clock to be able to capture the unit contains the first four interrupts INT4, and then capture module initialization and CAN controller initialization. Before the description of the content. As the capture unit is an interrupt from the capture FIFO stack will take a capture cycle value of the operation unit in the capture interrupt handler to; and CAN controller is in check form, to capture the main program loop check mark. Confirmed after capture, remove from the temporary register CAP4TEMP capture cycle value sent to the mailbox 3. It is worth mentioning that, due to capture cycle value of 16-bit data, it needs to transmit data is 2 bytes. So send the controller MSGCTRL3 the DL = 2. This process flow shown in Figure 2.

DSP and CAN bus transmission speed and the integration of remote

3.2 Capture Unit CAN controller, interrupt handling, including the information sent

As mentioned earlier, when the CAN controller is in query modalities, CAN controller's operating procedures are complex, but also in the main program is not conducive to the main program of expansion and increased peripheral; therefore CAN controller can send the information to set in Capture interrupt processing unit, so the main program becomes very simple. In this case, the capture unit to capture interrupt handler also include periodic removal and CAN messages. By reducing and recycling judge, CAN messaging simple. Capture Unit interrupt handler as follows:

CAP4_ISR
LDP # DP EVB
LACL CAP4FIFO; take to capture the value stack
LDP DP_USER
SACL CAP4TEMP; capture values into the temporary register
LDP # DP EVB
SPLK # 0, T3CNT; clear T3 counts, to re-count
LDP # DP_CAN
SPLK # 0000H, MDER;-mail not to be able to
SPLK # 0100H, MCR; CDR = I, the data change request
LDP # 5
LACL CAP4TEMP; take to capture the value
LDP # DP_CAN2
SACL MBX3A; to capture the value moved to the mailbox 3
LDP # DP_CAN
SPLK # 0880H, MCR; DBO = 1, CDR = 0, ABO = 1, STM = 0
SPLK # 08H, MDER; MD3 = 0, ME3 = 1, 3 to send the enable mailbox
LDP # DP CAN
SPLK # 0020H, TCR; mail send a request 3
W_TA3 LDP # DP_CAN
BIT TCR, 2; Email 3 Send response TA3 (bit 13) = 1
BCND W_TA3, NTC; wait to send response
LDP # DP_CAN
SPLK # 2000h, TCR; send the response was a reduction TA3
CLRC INTM; open break
RET

4 Conclusion

Analysis and design of that class TMS320LF407 using SoC chip features, the corresponding unit properly configured, will be simple, effective way to achieve speed faster control functions, Tixian the control, reflecting the control implementation Fangfa an inevitable developing trend. Debug application notes, the method is correct and effective