CAN bus Bit Timing Parameters

Abstract: CAN communication, the baud rate, bit period and location of sampling points can be programmed settings, those settings to the users to optimize network performance to provide a convenient communication. Optimization of bit timing parameters, to ensure that information synchronized, ensuring transmission delay and the clock error is carried out under extreme conditions appropriate error detection. This article describes the method for determining the bit timing parameters.

Introduction

CAN bus is an effective support for distributed control and real-time control, multi-master asynchronous serial communication network. As the CAN bus has a strong error correction capabilities, support for differential transceivers suitable for high noise environment, with far transmission distance, and Philips, and Intel and other semiconductor companies have integrated support for CAN communication protocol device. CAN bus has been in various fields has been widely used.

Specified in the CAN communication protocol, communication baud rate, each bit period the number of sampling locations and are free to set. This design concept for the user in their own applications, optimizing network performance to provide a space for communication. In order to set the bit timing parameters through the optimization of network traffic performance, bit timing parameters must be clear and the reference clock signal delay error and the relationship within the system. If the bit location of partial sampling period, it will be able to tolerate large signal transmission delay, the corresponding bus and the transmission distance can be extended; and if the period of sampling location close to the middle, you can tolerate the system reference clock error between nodes . But this is clearly contradictory, in order to coordinate such contradictions, we must optimize the parameters of the position of the bit timing.

CAN bus Bit Timing Parameters

Through the CAN bus bit timing parameters studied, to find the key to conflict, we can optimize it, to improve the overall performance of communication systems. The following independent communications company with Philips controller SJA1000, for example, were studied.

1 related definitions

1.1 cycle, the composition of the

Baud rate (fbit) is the unit time by the number of bits transmitted, and generally the unit of time is 1s. Baud rate transmitted by the communication line the length of a data bit period (Tbit) decided that example is shown below.

Fbit = 1/Tbit (1)

According to Philips the company's independent communications controller, a bit cycle from three components: the synchronization segment (tSYNC_SEG), the phase buffer segment 1 (tTSEG1) and the phase buffer segment 2 (tTSEG2).

Tbit = tSYNC_SEG + tTSEG1 + tTSEG2 (2)

All of these time periods, there is a common time unit - the system clock cycle (TSCL). Specific to the SJA1000, TSCL by the bus timing register values to determine. SJA1000 has two bus timing registers, the bus timing register 0 (BTR0) and the bus timing register 1 (BTR1). The two registers have their own definition of the different functions together determine the role of the communication bus baud rate.

Bus Timing Register 0 defines the baud rate default value BRP (a total of 6, values of the interval [1,64] and the synchronization jump width of SJW (a total of 2, values interval [1,4]) value. Bit functions Description as listed in Table 1.

Table 1

bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
SJW.1 SJW.0 BRP.5 BRP.4 BRP.3 BRP.2 BRP.1 BRP.0

CAN system clock cycle TSCL, can be decided by the BRP value as calculated using the following formula:

TSCL = 2TCLK × BRP = 2TCLK × (32BRP.5 +16 BRP.4 +

8BRP.3 +4 BRP.2 +2 BRP.1 +1 BRP.0 +1) (3)

TCLK as the reference time of one cycle.

TCLK = 1/fCLK (4)

Bus controller to compensate for different clock oscillator phase offset between any bus controller must send the relevant signal edge of the current re-synchronization. Synchronization jump width defines each cycle can be shortened or extended re-synchronize the maximum number of clock cycles.

tSJW = TSCL × (2 × SJW.1 +1 × SJW.0 +1) (5)

Bus Timing Register 1 defines the length of each bit period the location of sampling sites and sampling at each sample point number. Digital features such as Table 2 shows, in which SAM significance in Table 3.

Table 2

bit bit bit bit bit bit bit bit
SAM TSEG2.2 TSEG2.1 TSEG2.0 TSEG1.3 TSEG1.2 TSEG1.1 TSEG1.0

Table 3

Bit value function
SAM 0 three times: three times the bus sampling: proposed medium / low speed bus (A and B class) to use, there are bus glitch filter
1 Single: Bus sampling time; recommended for use in high-speed bus (SAEC level)

TSEG1 (total of 4, values of the interval [1,16]) and TSEG2 (a total of 3, values interval [1,8]) determines the number of each clock and the sampling point location. Here

tSYNC_SEG = 1 × TSCL (this time constant) (6)

tTSEG1 = TSCL × (8 × TSEG1.3 +4 × TSEG1.2 +2 × TSEG1.1 +1 × TESG1.0 +1) (7)

tTSEG2 = TSCL × (4 × TSEG2.2 +2 × TSEG2.1 +1 × TESG2.0 +1) (8)

Bit period of the scalar value (NBT) is defined as, SYNC_SEG (paragraph system synchronization clock cycles), TSEG1 (phase buffer segment 1 system clock cycles), TSEG2 (phase buffer segment 2 system clock cycles) of and. This determines the value of its interval [3,25], in a sampling point, the minimum generally take 4; in the three sampling points, the minimum usually take 5.

NBT = Tbit / TSCL = SYNC_SEG + TSEG1 + TSEG2 (9)

The general structure of a bit period as shown in Figure 1.

1.2 Reference Clock error

In the system, each node has its own separate reference clock. As the manufacturing process, running time and ambient temperature changes, the actual frequency of these clock frequencies often deviate from the expected value. We call this bias as the reference clock error (Δf). FCLK, max / min, said reference clock frequency of the maximum or minimum value, fCLK, rat said reference clock frequency rating.

Corresponding system clock cycle there will be errors. TSCL, min said the system clock cycle minimum, TSCL, max the maximum value that the system clock cycle, TSCL, rat, said system clock cycle rating. Since Δf <<1, can be approximate.

TSCL, min = (TSCL, rat) / (1 + Δf) ≈ TSCL, rat × (1-Δf) (11)

TSCL, max = (TSCL, rat) / (1-Δf) ≈ TSCL, rat × (1 + Δf) (12)

1.3 Propagation Delay

CAN bus using non-destructive arbitration mechanism based on priority. In this mechanism, the transmission delay is essential. If the transmission delay time is too long, will result in an invalid access arbitration. Transmission delay time from the physical bus delay (tBUS), bus driver delay (ttran) and other equipment propagation delay (toth) jointly decided. Other facilities include a communications controller, such as optocoupler isolated.

tprop = 2 × (tBUS + ttran + toth)

Propagation delay of the standard value (PROP) to the equation (14) are.

PROP = tprop / TSCL (14)

1.4 Synchronization

Through the synchronization mechanism to eliminate the impact of phase error to ensure the information is correct decoding. There are two simultaneous ways: hard synchronization and resynchronization.

Hard synchronization occurs only in the message began, in an idle period, all the controllers on the bus segment in a SYNC_SEG dominant from recessive bit to bit transitions along on their own bit initialization cycle time, execution time Hard synchronization.

Resynchronization occurred in the message sent during the bit stream, every hidden bit to the dominant position after the jump along. Resynchronization synchronization according to the edge of the phase error caused by either increased tTSEG1, or reduce the tTSEG2, so that sampling points in the proper place. Edge of phase synchronization error e, the edge relative to the synchronization depends on the location to the system clock cycle (TSCL). Other fixed and re-synchronization as follows:

e = 0, synchronization occurs in SYNC_SEG inside edge;

e> 0, synchronization occurs in TSEG1 inside edge;

e <0, synchronization occurs in TSEG2 inside edge.

If re-synchronization caused by the edge of the magnitude of the phase error e is less than or equal to tSJW programming values, the synchronization may lead to shortened or extended position, the role of synchronization with the same hardware; if e is positive, and the amplitude is greater than tSJW, increased tTSEG1 value tSJW; if e is negative, and the amplitude is greater than tSJW, decreased value of tSJW.

2 parameter calculation rules

Parameters principles: to ensure that the system in extremely harsh conditions of the two nodes can correctly receive and decode the information on the network frame. Extreme conditions is the Restructure of the two nodes in the system deviation of the two ends of the limit of tolerance deviation, and the two nodes have the maximum propagation delay. In the absence of noise the normal communication circumstances, the phase error accumulated in the worst case, the re-synchronization interval between the edge 10-bit cycle. This is the definition of minimum conditions for SJW.

In real communication systems, noise is inevitable. As the noise may lead to re-sync interval between the edge of more than 10-bit cycle, may enter the error handling mode. In this case, owing to synchronization edges longer between 時間, Suo Yi ensure that every one is really sure of the Di sample the more important. If you can not exactly sample, would lead to detect errors and for error handling.

Consider all the implications, bit timing parameters set formula is as follows:

① 1 sample point pattern

CAN bus Bit Timing Parameters

CAN bus Bit Timing Parameters

② 3 sampling point pattern

CAN bus Bit Timing Parameters

When calculating the SJWmin, take the smallest integer greater than the calculated values; in the calculation of TSEG2max time, take the greatest integer less than the calculated values. By the formula (15) ~ (18) can be seen, SJW and TSEG2 by the NBF, Δf, PROP were decided. After SJW and TSEG2 calculated by the formula (9) can be TSEG1. According SJA1000 register shows the specific register can be set values.

3 parameter calculation steps and examples

A CAN communication system, using a sample point pattern, other parameters indicators in table 4.

Table 4

Parameter Description Minimum Maximum Typical
fBit / (kb · s-1) communication baud rate 250
tbit / μs cycle time 4-bit
fCLK / MHz CAN controller clock frequency of 24
Δf /% clock frequency deviation of 1.0
tran / ns bus driver delay 3075157
toth / ns delay other equipment 15 40
δ / (ns · m-1) line delay 5 6.5
L / m bus length of 395 nodes
tBUS / ns delay line calculated tBUS = L · δ 15 618
fprop / ns propagation delay calculated by the formula (13) 1201630

① identify possible BRP, NBT and PROP.

By the formula (1), (3), (4) and (9) are

NBT = 1 / (fbit · TSCL) = fCLK / (2fbit · BRP)

So there NBT · BRP = fCLK/2fbit (19)

The parameters into the formula (19) by NBT · BRP value of 48, while the NBT value of 3 to 25, so NBT and BRP all the possible combinations listed in Table 5.

Table 5

fCLK NBT BRP TSCL / ns PROPmax PROPmin effectiveness
24MHz 4 12 1000 1.63 0.12 No
68 666.6 2.45 0.18 No
86 500 3.26 0.24 No
12 4 333.3 4.89 0.36 a
163 250 6.52 0.48 a
242 166.6 9.78 0.72 No

② Calculation NBTmin and NBTmax. By the formula (15-1), (18-1), (19), (14) and (3) introduced

CAN bus Bit Timing Parameters

NBT ≥

CAN bus Bit Timing Parameters

Incorporated into the data, calculated 8.31 ≤ NBT ≤ 17.9. In principle, selection 12 and 16 can be, for the convenience of obtaining samples, we choose the larger value of 16.

③ According to the formula (15-1) computing SJWmin, as shown in table 6.

④ According to the formula (17-1) computing TSEG2min, as shown in table 6.

⑤ According to the formula (18-1) computing TSEG2max, as shown in table 6.

⑥ register settings to determine value, as listed in Table 7.

Table 6

Determine the value of the minimum maximum
SJW (3.23,3.67) max 4 4
TSEG2 (2, SJW) max (8,5.54,4.78) min 4
TSEG1 TSEG1 = NBT-TSEG2-SYNC_SEG = 16-4-1 11

Table 7

BTR0 SHW BRP BTR1 SAM TSEG2 TSEG1
C2 1 1 0 0 0 0 1 0 3A 0 0 1 1 1 0 1 0

4 Conclusion

Systems in different applications, according to Suo Shi Yong's clock frequency, the clock signal's frequency deviation, communications baud rate and maximum transmission distance Deng factors, right communication controller Wei regular Canshujinxing optimization OK. Determine the parameters obtained can improve the overall performance of communication systems, which makes more obvious advantages of CAN bus in order to fit more widely used.