CAN bus based on the non-intelligent adapter card design

Controller Area Network CAN (Controller Area Network) is currently approved as international standards, one of a small number of field bus. CAN network can use multi-master manner. It uses non-destructive arbitration bus technology, signaling and control with a short frame structure, which has strong anti-interference ability and low coupling; CAH network traffic rates ranging from 5 kbs/10 km ~ lMbs / / 40m , drive up to 110 nodes. It is the transmission medium can be twisted pair, coaxial cable or fiber, choose a very flexible; information for each frame has a CRC checksum and other error detection measures, and thus the data error rate is very low, reliability is high; when its transmission serious error message when the node can automatically disconnect and bus links, so that other operations on the bus is not affected.

Although PCI, USB and other bus technology has been rapid development, but a large number of applications in computer and industrial computer test, the most used or ISA (Industry Standard Architecture. Industry Standard Architecture) bus. ISA-bus with 16-bit data width, the maximum operating frequency of 8MHz, the data transfer rate up to 16MB / s, there are 24 address bus, 16MB of address addressable unit, the bus signal is divided into five categories, namely address lines, data lines, control lines, clock lines and power lines.

To address the CAN controller SJA1000 with the ISA bus with the signal lines and logic with timing problems, the author designed a CAN bus based on the non-intelligent adapter card. The adapter card has been used in the author developed "based on CAN-bus Motion Control System", run well.

Non-intelligent ISA bus adapter card, the overall structure of CAN

CAN controller SJA1000 address data bus is time division multiplexing, and by the falling edge of ALE signal can be latched on the address bus signal; ISA bus address and data bus are provided independently, it can not address directly and SJA1000 data bus. This design using address decoding circuit for decoding the address signal line so as to allocate a certain CAN adapter's port address. Then, use the 74HC373 chip latches the data latch function for the first time I / O operations through the ISA data bus transmission of data signals, so as to access CAN controller SJA1000 in the register address signal, and finally in the second I / O operations the completion of the corresponding address register SJA1000 reading and writing. The overall structure of its adapter shown in Figure 1.
74HC373 address latch port address can be seen as SJA1000 and SJA1000 SJA1000 data itself can be regarded as the port, in addition to hardware reset of the SJA1000 the reset port. Map the base address decoding circuitry to enable signal AEN as on the A2 ~ A9 address signal decoding can be the base adapter addresses; combinations available AO and A1 address signal offset of the port. SJA1000 is used for communication with the ISA of the two I / O operation, the first of a first delivery address to the address port, the second and then the data port access. Mentioned here are the address and data ports on the SJAl000 purposes, the data line through the ISA bus is available to access the SJA1000 register address and the transmission of data. Control port decoding circuit can be sent by CPU control signals and address signals at a certain combination of logical relations to generate a new set of function signals as the interface control signal. SJA1000 reset by reset circuit can SAJ1000 specific operation can be used on reset, the program reset button reset and hardware reset of three ways.

Adapter hardware design

Base address decoding circuit

Figure 2 shows the base address of a specific decoder. Under normal circumstances, according to system needs, address decoding circuitry on the ISA address lines of port address decoding, and AO ~ A9 can be expressed. Base address decoding circuitry on the A9 ~ A2 decoding, may act as a port on the card base address.

CAN bus based on the non-intelligent adapter card design

Figure 2, 74HC688 is an 8-bit comparator value, then Pi = Qi (i = 0 ... 7), P = Q of the anti-ended output low. When the ISA bus of the AEN is high, the bus working in DMA mode; time when AEN is low, CPU has control of the bus. Non-intelligent adapter cards is actually the CPU on the working process I / O operation process, during which, AEN is always low, can be used to control the strobe terminal G 74HC688 counter. Only in the I / O operation, it allows it to select the address. The use of the DIP switch, users can pre-set base address of adapter cards. The offset of each port on the card from the A1 and A0 select, and through software control, the design definition of offset address port 00, the data offset port 01, reset the port offset 11.

Control Signal

The adapter card of the control signal generation circuit shown in Figure 3. The circuit's main role is sent to CPU control lines and address lines of logic according to certain combination, to generate a new set of function signals Shu Chu. The signal can be used as interface control signals to control the SJA1000, 74HC373, 74HC245 chips such as the work of the state. Since the base address decoder circuit output signal for the P = Q of the anti-(active LOW), SJA1000 address port offset address 00H, the data port offset address 01H, therefore, according to control logic, each adapter card chip control signal logic expression is:

CAN bus based on the non-intelligent adapter card design

CAN bus based on the non-intelligent adapter card design

In the course of adapter cards, the chip's logic timing relationship is this: when the output data valid 74HC373, 74HC245 output is high impedance state; when the 74HC373 output showed a high impedance state, and SJA1000 to ISA bus data directly back to the time, 74HC245 input and output is working properly. Specifically, assuming CAN base address 300H, and visit the SJA1000 is in two I / O operation is complete, then the first data sent to port 300H can be written after the signal is locked along there 74HC373, this operation, 74HC245 and 74HC373 E, the LE side effectively, but the OE terminal is high 74HC373, 74HC373 output high impedance state; when the second time when access to the data port 301H, SJA1000 is selected, then CPU can The corresponding unit of the SJA1000 read / write operations. Specific operational process is divided into reading and writing both. When the second time I / O operation arrives, SJA1000 falling in the BALE signal the first time I / O operation, lock the data as there 74HC373 address latch, the process, 74HC245 anti-E, is high, output was high impedance state, 74HC373's OE is low against the output side effective, to transmit address signals SJA1000. When the address is latched after the SJA1000, at this time if there is to read, then read the signal in the effective period (low), 74HC373's output to allow for the high end anti-OE, 74HC373 output showed a high impedance state, which SJA1000 can be selected when the unit register contents to the data output bus, and drive into the CPU, through the 74HC245. Latch in the address after the write operation if there is, then, 74HC373 output allows side always effective, then you can write the signal in the effective period, the corresponding write data SJA1000 unit.
Computer through the ISA bus of the CAN controller SJA1000 read and write timing are shown in Figure 4 and Figure 5.

CAN bus based on the non-intelligent adapter card design

Reset Circuit

SJA1000 work before, only through the reset pin of its reliable hardware reset to the register of the SJA1000 make the correct read and write operations. So that a reliable reset SJA1000 minimum level continuous time 0.1μs, PC system level reset the duration of up to several microseconds. System, the system reset signal RESET is high when the power supply connected through inverter can be directly used to reset the SJA1000. Figure 6 shows the adapter card, reset circuit, the reset of the SJA1000 has a boot on reset, the program reset and reset button three ways.

CAN bus based on the non-intelligent adapter card design

In Figure 6, A1 and A0 through NAND gate 74LSl0, in order to generate the offset address of reset circuit 11, the address signals and IOW Counter, P = Q signal through the logic combination of anti-so, and to support programs designed to generate SJA1000 reset signal. Program designed to write only port on a data reduction procedure can be realized reset. The reset button can be run in the system when communication failures occur, directly on the CAN controller SJA1000 hardware reset.

Adapter Software

The key part of the software design is the design of CAN communication program. Communication process (process shown in Figure 7,8,9) can be divided into three parts: CAN initialization, receiving process, send process. Initialization is a prerequisite for communication, mainly to complete some of the CAN controller register settings. As the SJA1000 interrupt operations support, so you can interrupt service routine to complete the receive and transmit data to improve system efficiency.

In fact, only in the reset mode can be initialized on the SJA1000, initialization includes work settings, receive filter mode setting mask register and receive the code to receive register set, the baud rate parameter setting and interrupt Allow register settings. After the completion of initialization can be set to work SJA1000 state to carry out normal communications. Subroutine is responsible for node to send packets to send. Send when you read the status register and determine appropriate, and send the data to be combined into a specific format for a message, send the buffer zone into the SJA1000, SJA1000 and then start to send; received message subroutine is responsible for the node reception and treatment of other conditions. In dealing with the process of receiving messages, but also on the bus off, error alarm, receive overflow handling the situation.

CAN adapter interrupt communication with the computer can use. However, WIN API can not directly control the break, only the underlying operating system CAN adapter for the preparation of the virtual device driver (VxD) can use interrupts. This requires a virtual device driver will interrupt virtualization, and response functions in the interrupt event to write the necessary code, while providing access interface for applications. It should be noted: the computer through the ISA bus right on the SJA1000 CAN adapter uses a visit to two I / O operations, for the first time Wang address port to send address, the second on the data port access. The detailed codes are as follows:

/ / To the specified SJA1000 register (address addr) write a byte of data (data), CAN_BASE as the base address
void CanIRQ:: writeByte (int CAN_BASE, unsigned char addr, unsigned char data)
(
_outp (CAN_BASE, addr);
_outp (CAN_BASE +1, data);
)
/ / From the specified SJA1000 register (address addr) read a byte of data (data)
unsigned char CanIRQ:: ReadByte (int CAN_BASE, unsigned char addr)
(
unsigned char result;
_outp (CAN_BASE, addr);
result = _inp (CAN_BASE +1);
return result;
)

Visit SJA1000 program, you can directly call these two Functions. In this way, send the segment code:

Bool CanIRQ:: CanTrans (int CAN_BASE, unsigned char * pTransBuf)
(
status = ReadByte (CAN_BASE, SR); / / SR for the status register address
for (i = 0; i
(
WriteByte (CAN_BASE, * pTFansBuf, ptbuf; / / pTransBuf to send buffer address
ptbuf + +; pTransBuf + +;
)
)

Conclusion

ISA bus by addressing the computer and CAN controller SJA1000 with the logic of coordination and timing to be completed by non-intelligence based on CAN Bus Adapter. The adapter has been successfully applied to the author by the development of CAN bus-based measurement and control system. In fact, if the increase in the adapter card CAN communication controller, you can get more than a cassette CAN bus, to increase the network node, expand the network scale. In addition, you can also adapter applications, depending on the application system requires the preparation of various control procedures to extend the system functionality.