CAN bus interface controller and the DSP

Abstract: This paper discusses CAN bus interface between controller and DSP, introduced the popular SJA1000 CAN controller chip and the TMS320 series DSP chip interface timing, and given their interface method and circuit.

Fieldbus is an open, digital, multi-point communications in local area network control system, most of today's automation technology with the application prospect of one. CAN bus is a fieldbus application hot spots, CAN bus support for distributed control and time control serial communication network. As the CAN bus with communication rate is high, open and good, short packets, error correction ability 以及 simple to control, expand capacity, low cost system, more and more attention. CAN controller based on CAN bus CAN bus communication protocol has completed all the necessary functions required, so CAN controller interface with other microprocessor design of CAN bus system as top priority. Currently there are a number of microprocessors will be embedded CAN controller to the system to become part of film making in the processor, for example, P8XC592 (the core shall be 80C51's CPU), MCS96 series 87C196CA, 87C196CB, TMS320 series In the film CAN microcontroller TMS320LF2407, TMS320F2810/F2812, but there are still a lot of people are not familiar with CAN controller microprocessor. This article discusses the microprocessor controller with CAN interface issues, focusing on TMS320 series DSP CAN controller and interface methods and interface circuit.

CAN bus interface controller and the DSP

1 CAN controller interface signals and timing

CAN controller (SJA1000 to PCX82C200 or example) for the microprocessor interface signals are mainly AD0 ~ AD7 total of eight address data lines and ALE, CS, RD, WR, RST, MODE, RESET and INT, the controller time-multiplexed data and address lines, which interface mode selection signal MODE to be used or in MODTOROLA INTEL way. Different ways as defined in Table 1 under the pin, interface timing shown in Figure 1 and Figure 2.

Table 1 SJA1000 pin definition

Pin Symbol INTEL (MODE = Vdd) MOTOROLA (MODE = Vss)
ALE ALE AS
RD RD E
WR WR RD / WR

From the pin definitions and known timing relationships with INTEL CAN controller mode and direct mode of interface signals MOTOROLA, INTEL manner in which the current popular 51/96 series of microcontroller provides a convenient and efficient for direct interface design.

CAN bus interface controller and the DSP

2 DSP interface signals and timing

TI DSP chips to produce TSM320 series of products for the mainstream product, TSM320 series has gone through several generations, have''C1X'','' C2X,''C2XX,''C5X,''C54X,'' C62X and other fixed-point DSP, a''C3X,''C4X,''C67X and other floating-point DSP and''C8X multi-processor DSP. DSP uses an advanced Harvard structure, internal multi-bus architecture and assembly line work methods, and thus greatly improve the system run faster and digital signal processing capabilities, DSP's Zhilingzhixing Shijian in ns Shu Liang Ji, internal program and data memory currently Yi up to tens of K words, and with internal hardware multiplier, the DSP has provided a broad application space.

DSP chip chip pin generally use the address lines and data separation design, without using time-multiplexed address data line, there is no effective signal ALE addresses, so give CAN controller and the DSP interface made it difficult to , and different DSP chip external pins and timing are slightly different. CAN controller and the DSP to design the interface, we must first discuss the DSP timing, following the more popular with DSP TMS320VC5402 TMS320LF2407 and case discussion.

CAN bus interface controller and the DSP

2.1 TMS320LF2407 DSP's I / O timing

DSP's memory is divided into three spaces: program memory space and data memory space and I / O space. I / O space dedicated input commands and output commands PORTW PORIR and dedicated I / O space select signal IS, TMS320LF2407 the I / O signals and the memory operation signal multiplexing, which is memory and I / O device strobes STBR write strobe WR, read strobe RD and write signal R / W, TMS320LF2407 the I / O timing shown in Figure 3 and Figure 4.

CAN bus interface controller and the DSP

2.2 TMS320VC5402 DSP's I / O timing

TMS320VC5402 and TMS320LF2407 the same, with IS as the I / O space select signals, difference is I / O space dedicated I / O device strobes IOSTRB and general literacy signal R / W, instead of being read strobe No. RD and the write strobe WR, its timing as shown in Figure 5 and Figure 6.

2.3 DSP's I / O Timing Analysis

I / O for input or output duty cycle is generally completed within two machine cycles, during, IS signal and address bus has been effective. For TMS320LF2407, I / O strobe signals STRB in the first effective after the machine cycle and continued for more than one machine cycle, RD and WE valid data effectively. For the TMS320VC5402, I / O device strobes IOSTRB the low effective delayed by half in the rising edge of the machine cycle to the next rising edge of a machine cycle, for one machine cycle, the data effectively in the second machine cycle in. R / W signal is input to read and write cycle has been maintained at "1", the output cycle has been maintained at "0", only play a role in controlling the direction of data flow. The above analysis period, each time I / O operations are to extend the machine cycle, which requires three machine cycles to complete I / O operations (wait cycle timing omitted).

CAN bus interface controller and the DSP

3 CAN controllers and DSP interface design

Seen from the above analysis can be divided, TMS320 series DSP with SJA1000 CAN controller does not provide a direct interface signals to the INTEL SJA1000 an example, in order to meet the SJA1000 TMS320 series DSP interface signal requirements of the design from the following .

3.1 Address data lines design reuse

The DSP data lines D0 ~ D7 as CAN address / data multiplexed lines, data lines used to select the DSP's internal CAN ports and transfer data.

3.2 Address valid signal generation ALE

CAN bus interface controller and the DSP

For TMS320LF2407, with address lines A0, write strobe WR and the port strobe STRB DSP logic combination of the ALE signal generated for the TMS320VC5402, then use the address lines A0, I / O port logic IOSTRB strobe combination produces ALE signal.

3.3 read and write signals generated

For TMS320LF2407, with the reading of the logical combination of signals and A0 produced SJA1000 the read strobe, with the write signal and the logical combination of A0 produced SJA1000 write strobe. For the TMS320VC5402, the use of A0, IOSTRB and R / W logic combination produces SJA1000 to read and write strobes. Logic as shown in Table 2.

Table 2 TMS320LF2407 and TMS320VC5402 and SJA1000 interface logic

TMS320LF2407 TMS320VC5402 SJA1000
A0 STRB R / W WE A0 IOSTRB R / W ALE WE RD
1 0 0 X 1 0 0 1 1 1
0000000001
0011001010

3.4 select signal generation

With the DSP's I / O space strobe signals IS and the high address decoding logic combination of signals generated on-chip CAN choose CS.

Design can be seen from the above, this approach is the data line to meet the DSP CAN controller data address lines. DSP-A0 as this will select the line address data. A0 = 1, the address is valid; A0 = 0, the data effectively. Select the port with an odd number address that is used to transmit data even address. Meanwhile, the signal logic combination of the effective period of the address signal does not produce read and write, but from the address valid to meet the CAN signal ALE; generated during the data valid logic signal to meet the CAN read and write timing.

CAN bus interface controller and the DSP

4 CAN interface circuit with the DSP

TMS320VC5402 and SJA1000 to design the interface circuit chip as an example shown in Figure 7. In the figure, with a GAL16V8B as the interface logic circuit. To highlight the interface circuit, other parts omitted. FM write design documents with the following:

GAL16V8B
INTERFACE
CH SH APR 19,20002
DECODER
NC NC IS IOSTRB A0 RW A14 A15
NC GND
NC NC CS WR RD ALE NC NC NC VCC
CS = A15 * A14 * IS
ALE = A0 * IOSTRB * R / W
RD = A0 * IOSTRB * R / W